1. Field of the Invention
The present invention generally relates to a driving device using a CMOS inverter, and more specifically, to a driving device using a CMOS inverter which can perform a stable operation due to a compensating circuit for compensating variations caused by changes of process conditions or external environments are changed.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a delay circuit using a conventional CMOS inverter.
The delay circuit of FIG. 1 comprises inverters IV1˜IV4 connected serially. An input signal IN is sequentially inverted by inverters, and outputted as an output signal OUT. Here, the number of inverters determines a phase of the output signal OUT. That is, when the odd number of inverters is used, the phase of the output signal OUT opposite to that of the input signal IN is delayed. When the even number of inverters is used, the phase of the output signal OUT identical with that of the input signal IN is delayed.
The basic operation of the inverter is performed by inter-compensation effect of a NMOS transistor and a PMOS transistor that form an inverter. If one of process factors or external environment in the two transistors is changed, their characteristics are affected.
As a result, although only using digital signals can perform the normal operation, the above variation may interrupt the normal operation when the timing is regulated or the oscillation having a predetermined cycle is required.
FIG. 2 is a circuit of an oscillator using a conventional CMOS inverter.
The oscillator of FIG. 2 comprises inverters IV5˜IV9 connected serially. An output terminal of the inverter IV9 is connected to an input terminal of the inverter IV5.
FIGS. 3A to 3C are timing diagrams illustrating the operation when the process condition and the environment condition of the oscillator are simultaneously changed.
FIG. 3A is a timing diagram illustrating the normal mode at 25° C. FIG. 3B is a timing diagram illustrating the fast mode at −5° C. Here, in the fast mode, the NMOS transistor and the PMOS transistor are manufactured at the process condition where they operate fast. FIG. 3C is a timing diagram illustrating the slow mode at 85° C. Here, in the slow mode, the NMOS transistor and the PMOS transistor are manufactured at the process condition where they operate slowly.
As described above, when the oscillator is embodied only with an inverter, the delay time is changed depending on the process condition.
In order to reduce the variation, a passive device that has relatively low process variations is connected between inverters.
FIG. 4 is a circuit diagram illustrating another example of the delay circuit using a conventional CMOS inverter.
The delay circuit of FIG. 4 comprises inverters IV11˜IV14 and resistors R1˜R3 which are alternately connected in serial. NMOS type capacitors NC1, NC2 and NC3 are connected to output terminals of the inverters IV11, IV12 and IV13 and PMOS type capacitors PC1, PC2 and PC3 are connected to input terminals of the inverters IV12, IV13 and IV14, respectively.
In the above-described example, the resistors R1˜R3 and the capacitors NC1.about.NC3 and PC1.about.PC3 are used to reduce the change of inverter characteristics resulting from change of the CMOS transistor comprised in an inverter.
However, the area of the chip increases because the resistor uses an active surface or a gate layer and the capacitor uses a gate capacitor.
Furthermore, although the characteristics of the passive device is not changed by the process condition or external environment, it is impossible to compensate the current variation because current which determines the operating characteristics flows through the CMOS transistor comprised in an inverter.